Exemplary embodiments relate to a method of discharging unselected strings when a program operation is performed.
FIG. 1 is a circuit diagram of a memory block.
A semiconductor memory device includes a memory cell array for storing data. The memory cell array includes a plurality of memory blocks. A memory block is described below in detail as an example.
The memory block includes a plurality of cell strings ST. Each of the cell strings ST includes a drain selection transistor DST, a source selection transistor SST, and a plurality of memory cells F0 to Fn coupled in series between the drain selection transistor DST and the source selection transistor SST. The drain of the drain selection transistor DST is coupled to a bit line BL, and the source of the source selection transistor SST is coupled to a common source line CSL. The gates of the drain selection transistors DST included in the respective strings ST are interconnected to form a drain selection line DSL, and the gates of the source selection transistors SST included in the respective strings ST are interconnected to form a source selection line SSL. The gate electrodes of the memory cells F0 to Fn included in the respective strings ST are interconnected to form a plurality of word lines WL0 to WLn.
FIG. 2 is a timing diagram illustrating a conventional program operation.
Referring to FIGS. 1 and 2, the program operation includes a precharge period in which a bit line is precharged, a channel boost period in which the channel voltage level of a string is raised, a program period in which the threshold voltages of selected memory cells are raised, and a discharge period in which a channel and bit lines are discharged.
At a point of time T1 when the precharge period starts, a precharge-inhibition voltage is supplied to an unselected bit line Unsel_BL. The precharge-inhibition voltage may be a power supply voltage Vcc. Although not shown, a voltage 0V of a ground voltage level is supplied to a selected bit line.
At a point of time T2, when the voltage of the unselected bit line Unsel_BL reaches the power supply voltage (Vcc) level, the drain selection transistor DST is turned on by supplying the power supply voltage to the drain selection line DSL. Thus, the power supply voltage Vcc supplied to the unselected bit line Unsel_BL is transferred to unselected strings and thus increases a potential level difference in the channel of the unselected strings (hereinafter referred to as a ‘channel potential’). As described above, the voltage transferred from the unselected bit lines Unsel_BL to the unselected strings is the power supply voltage. Accordingly, at a point of time T3 when the voltage of the drain selection line DSL reaches the power supply voltage (Vcc) level, the channel potential may rise up to a first voltage Vch1 of the power supply voltage (Vcc) level.
At a point of time T4 when the channel boost period starts, a pass voltage Vpass is supplied to a selected word line Sel_WL and unselected word lines Unsel_WL. When the pass voltage Vpass is supplied to the selected word line Sel_WL and the unselected word lines Unsel_WL, the channel potentials of the unselected strings rise owing to coupling between the word line and the channel and thus become a second voltage Vch2 higher than the first voltage Vch1. This is called channel boosting. Meanwhile, the channel boosting does not occur in a selected string coupled to a selected bit line to which a ground voltage is supplied.
At a point of time T5 when the program period starts, the program operation for raising the threshold voltages of selected memory cells included in a selected string is performed by supplying a program voltage Vpgm to the selected word line Sel_WL.
At a point of time T6 when the discharge period starts, the voltage supplied to all the word lines Sel_WL and Unsel_WL is lowered to a ground voltage level. That is, all the word lines Sel_WL and Unsel_WL are discharged. Here, the channel potential is also lowered with a reduction of the coupling between the word line and the channel.
At a point of time T7, the voltage supplied to all the word lines Sel_WL and Unsel_WL has dropped to the ground voltage level. However, the power supply voltage continues to be supplied from the unselected bit lines Unset_BL and the drain selection transistor DST remains turned on. Accordingly, the channel potential becomes lower than the level when the channel boosting occurred, but can maintain a level higher than the ground voltage level 0V.
At a point of time T8, the voltages supplied to the drain selection line DSL and the unselected bit lines Unsel_BL are lowered from the power supply voltage (Vcc) level to the ground voltage level. At this time, the channel potential is to be preferably lowered to the ground voltage level. However, if the drain selection line DSL is discharged and thus the drain selection transistor DST is turned off before the channel potential drops to the ground voltage level, the string becomes in a floating state with a voltage Vr remaining in the channel. In this case, a subsequent verification operation may not be accurately performed, thereby disturbing a normal program operation.
The time taken for the discharge period may be increased for the normal program operation. However, this method may increase the total operating time.